View CYBLE-214015-01_8719220.PDF datasheet online --- IC-ON-LINE

Datasheet File OCR Text:

preliminary CYBLE-214015-01 ez-ble? psoc ? bluetooth 4.2 module cypress semiconductor corporation ? 198 champion court ? san jose , ca 95134-1709 ? 408-943-2600 document number: 002-15923 rev. *b revised december 15, 2016 general description the cypress CYBLE-214015-01 is a fully certified and qualified module supporting bluetooth ? low energy (ble) wireless communication. the CYBLE-214015-01 is a turnkey solution and includes onboard crystal oscillators, trace antenna, passive components, and the cypress psoc ? 4 ble. refer to the psoc ? 4 ble datasheet for additional details on the capabilities of the psoc 4 ble device used on this module. the ez-ble ? psoc ? module is a scalable and reconfigurable platform architecture. it combines programmable and reconfigurable analog and digital blocks with flexible automatic routing. the CYBLE-214015-01 also includes digital programmable logic, high-performance analog-to-digital conversion (adc), opamps with comparator mode, and standard communication and timing peripherals. the CYBLE-214015-01 includes a royalty-free ble stack compatible with bluetooth 4.2 and provides up to 25 gpios in a small 11 11 1.80 mm package. the CYBLE-214015-01 is drop-in compatible with the cyble-014008-00 and cyble-214009-00 ez-ble modules. the CYBLE-214015-01 is a complete solution and an ideal fit for applications seeking a highly integrated ble wireless solution. module description module size: 11.0 mm 11.0 mm 1.80 mm (with shield) drop-in compatible with cyble-014008-00 and cyble-214009-00 256-kb flash memory, 32-kb sram memory up to 25 gpios configurable as open drain high/low, pull-up/pull-down, hi-z analog, hi-z digital, or strong output bluetooth 4.2 qualified single-mode module ? qdid: 79480 ? declaration id: d029646 certified to fcc, ce, mic, kc, and ic regulations industrial temperature range: ?40 c to +85 c 32-bit processor (0.9 dmips/mh z) with single-cycle 32-bit multiply, operating at up to 48 mhz watchdog timer with dedicated internal low-speed oscillator (ilo) two-pin swd for programming power consumption tx output power: ?18 dbm to +3 dbm received signal strength indicator (rssi) with 1-db resolution tx current consumption of 15.6 ma (radio only, 0 dbm) rx current consumption of 16.4 ma (radio only) low power mode support ? deep sleep: 1.3 a with watch crystal oscillator (wco) on ? hibernate: 150 na with sram retention ? stop: 60 na with xres wakeup programmable analog four opamps with reconfigur able high-drive external and high-bandwidth internal drive, comparator modes, and adc input buffering capability; can operate in deep-sleep mode 12-bit, 1-msps sar adc with differential and single-ended modes; channel sequencer with signal averaging two current dacs (idacs) for general-purpose or capacitive sensing applications on any pin one low-power comparator that operate in deep-sleep mode programmable digital four programmable logic blocks ca lled universal digital blocks, (udbs), each with eight macrocells and datapath cypress-provided peripheral co mponent library, user-defined state machines, and verilog input capacitive sensing cypress capsense sigma-delta (csd) provides best-in-class snr (> 5:1) and liquid tolerance cypress-supplied software component makes capacitive-sensing design easy automatic hardware-tuning algorithm (smartsense?) segment lcd drive lcd drive supported on all gpios (common or segment) operates in deep-sleep mode with four bits per pin memory serial communication two independent runtime reconfigurable serial communication blocks (scbs) with i 2 c, spi, or uart functionality timing and pulse-width modulation four 16-bit timer, counter, pulse-width modulator (tcpwm) blocks center-aligned, edge, and pseudo-random modes comparator-based triggering of kill signals for motor drive and other high-reliability digital logic applications up to 25 programmable gpios any gpio pin can be capsense, lcd, analog, or digital
preliminary CYBLE-214015-01 document number: 002-15923 rev. *b page 2 of 42 more information cypress provides a wealth of data at www.cypress.com to help you to select the right modu le for your design, and to help you to quickly and effectively integrate the module into your design. overview: ez-ble module portfolio , module roadmap ez-ble psoc product overview psoc 4 ble silicon datasheet application notes: cypress offers a number of ble application notes covering a broad range of topics, from basic to advanced level. recommended application notes for getting started with ez-ble modules are: ? an96841 - getting started with ez-ble module ? an94020 - getting started with psoc ? 4 ble ? an97060 - psoc ? 4 ble and proc? ble - over-the-air (ota) device firmware upgrade (dfu) guide ? an91162 - creating a ble custom profile ? an91184 - psoc 4 ble - designing ble applications ? an92584 - designing for low power and estimating battery life for ble applications ? an85951 - psoc ? 4 capsense ? design guide ? an95089 - psoc ? 4/proc? ble crystal oscillator selection and tuning techniques ? an91445 - antenna design and rf layout guidelines technical reference manual (trm): ? psoc ? 4 ble technical reference manual ? psoc(r) 4 ble registers technical reference manual knowledge base articles ? kba210574 - rf regulatory certifications for cy- ble-014008-00, cyble-214009-00, and cy- ble-214015-01 ez-ble? psoc? modules ? kba216236 - pin mapping differences between the ez-ble? psoc? evaluation board (cyble-214015- eval) and the ble pioneer kit (cy8ckit-042-ble) ? kba97095 - ez-ble? module placement ? kba213976 - faq for ble and regulato ry certifications with ez-ble modules ? kba210802 - queries on ble qualification and declaration processes development kits: ? cyble-214015-eval , CYBLE-214015-01 evaluation board ? cy8ckit-042-ble , bluetooth ? low energy (ble) pioneer kit ? cy8ckit-002 , psoc ? miniprog3 program and debug kit test and debug tools: ? cysmart , bluetooth ? le test and debug tool (windows) ? cysmart mobile , bluetooth ? le test and debug tool (android/ios mobile app) two design environments to get you started quickly psoc ? creator? integrated design environment (ide) psoc creator is an integrated design environment (i de) that enables concurrent hardware and firmware editing, compiling and debugging of psoc 3, psoc 4, psoc 5lp, psoc 4 ble, proc bl e and ez-ble module systems with no code size limitations. psoc peripherals are designed using schematic capture and simple graphical user inte rface (gui) with over 120 pre-verified, production-ready psoc components?. psoc components are analog and digital ?virtual chips,? represent ed by an icon that users can drag-and-drop into a design and configure to suit a broad array of application requirements. bluetooth low energy component the bluetooth low energy component inside psoc creator provides a comprehensive gui-based configuration window that lets you quickly design ble applications. the component incorporates a bluet ooth core specification v4.2 co mpliant ble protocol stack an d provides api functions to enable user applications to interfac e with the underlying bluetooth low energy sub-system (bless) hardware via the stack. ez-serial? ble firmware platform the ez-serial firmware platform provides a simple way to access the most common hardware and communication features needed in ble applications. ez-serial implements an intuitive api protoc ol over the uart interface and exposes various status and cont rol signals through the module?s gpios, making it easy to add ble functionality quickly to existing designs. use a simple serial terminal and evaluation kit to begin develo pment without requiring an ide. refer to the ez-serial webpage f or user manuals and instructions for getting started as well as detailed reference materials. ez-ble modules are pre-flashed with the ez-s erial firmware platform. if you do not hav e ez-serial pre-loaded on your module, yo u can download each ez-ble module?s firmware images on the ez-serial webpage . technical support frequently asked questions (faqs) : learn more about our ble eco system. forum : see if your question is already answered by fello w developers on the psoc 4 ble and proc ble forums. visit our support page and create a technical support case or contact a local sales representatives . if you are in the united states, you can talk to our technical support team by calling our to ll-free number: +1-800-541-4736. se lect option 2 at the prompt.
preliminary CYBLE-214015-01 document number: 002-15923 rev. *b page 3 of 42 contents overview............................................................................ 4 module description.................. .................................... 4 pad connection interface ................................................ 6 recommended host pcb layout ................................... 7 digital and analog capabilities and connections......... 9 power supply connections and recommended external components.................................................................... 11 connection options................................................... 11 external component recomm endation ......... ........... 11 critical components list ........................................... 14 antenna design......................................................... 14 electrical specification .................................................. 15 gpio ......................................................................... 17 xres......................................................................... 18 analog peripherals .... .............. .............. .............. ...... 18 digital peripherals ..................................................... 22 serial communication ............................................... 24 memory ..................................................................... 25 system resources .................................................... 25 environmental specifications ....................................... 31 environmental compliance ....................................... 31 rf certification.......................................................... 31 environmental conditions ......................................... 31 esd and emi protection ........................................... 31 regulatory information .................................................. 32 fcc ........................................................................... 32 industry canada (ic) certific ation ............................. 33 european r&tte declaration of conformity ............ 33 mic japan ................ .............. .............. .............. ....... 34 kc korea................................................................... 34 packaging........................................................................ 35 ordering information...................................................... 37 part numbering convention ..... ................................. 37 acronyms ........................................................................ 38 document conventions ................................................. 40 units of measure ....................................................... 40 document history page ................................................. 41 sales, solutions, and legal information ...................... 42 worldwide sales and design supp ort............. .......... 42 products .................................................................... 42 psoc? solutions ....................................................... 42 cypress developer community................................. 42 technical support .................. ................................... 42
preliminary CYBLE-214015-01 document number: 002-15923 rev. *b page 4 of 42 overview module description the CYBLE-214015-01 module is a complete module designed to be soldered to the main host board. module dimensions and drawing cypress reserves the right to select components (including the appropriate ble device) from various vendors to achieve the ble module functionality. such selections wi ll guarantee that all height restrictions of the component area are maintained. designs should be completed with the physical dimensions shown in the mechanical drawings in figure 1 on page 5. all dimensions are in millimeters (mm). table 1. module design dimensions see figure 1 on page 5 for the mechanical reference drawing for CYBLE-214015-01. dimension item specification module dimensions length (x) 11.00 0.15 mm width (y) 11.00 0.15 mm antenna location dimensions length (x) 11.00 0.15 mm width (y) 4.62 0.15 mm pcb thickness height (h) 0.80 0.10 mm shield height height (h) 1.00 0.10 mm maximum component height height (h) 1.00 mm typical (shield) total module thickness (bottom of module to highest component) height (h) 1.80 mm typical
preliminary CYBLE-214015-01 document number: 002-15923 rev. *b page 5 of 42 figure 1. module mechanical drawing top view bottom view side view note 1. no metal should be located beneath or above the antenna area. only bare pcb material should be located beneath the antenna ar ea. for more information on recommended host pcb layout, see figure 3 on page 6, figure 4 and figure 5 on page 7, and figure 6 and ta b l e 3 on page 8.
preliminary CYBLE-214015-01 document number: 002-15923 rev. *b page 6 of 42 pad connection interface as shown in the bottom view of figure 1 on page 5, the CYBLE-214015-01 connects to the host board via solder pads on the back of the module. ta b l e 2 and figure 2 detail the solder pad length, width, and pitc h dimensions of the CYBLE-214015-01 module. figure 2. solder pad dimensions (seen from bottom) to maximize rf performance, the host la yout should follow these recommendations: 1. the ideal placement of the cypress ble m odule is in a corner of the host board with the antenna located on the edge of the ho st board. this placement minimizes the additional reco mmended keep-out area stated in item 2. refer to an96841 for module placement best practices. 2. to maximize rf performance, the area immediately around th e cypress ble module trace antenna should contain an additional keep-out area, where no grounding or signal traces are contain ed. the keep-out area applies to al l layers of the host board. th e recommended dimensions of the host pcb keep-out area are shown in figure 3 (dimensions are in mm). figure 3. recommended host pcb keep-out ar ea around the CYBLE-214015-01 trace antenna table 2. solder pad connection description name connections connection type pad length dimension pad width dimension pad pitch sp 32 solder pads pad9/pad24: 0.74 mm all others: 0.79 mm 0.41 mm 0.66 mm host pcb keep-out area around trace antenna
preliminary CYBLE-214015-01 document number: 002-15923 rev. *b page 7 of 42 recommended host pcb layout figure 4 through figure 6 and ta b l e 3 provide details that can be used for the recommended host pcb layout pattern for the CYBLE-214015-01. dimensions are in millimeter s unless otherwise noted. pad length of 0. 99 mm (0.494 mm from center of the pad on either side) shown in figure 6 is the minimum recommended host pad length. the host pcb layout pattern can be completed using either figure 4 , figure 5 , or figure 6 . it is not necessary to use all figures to complete the host pcb layout pattern. figure 4. host layout pattern for CYBLE-214015-01 figure 5. module pad location from origin top view (seen on host pcb) top view (seen on host pcb)
preliminary CYBLE-214015-01 document number: 002-15923 rev. *b page 8 of 42 ta b l e 3 provides the center location for each solder pad on the cyble- 214015-01. all dimensions are refe renced to the center of the solder pad. refer to figure 6 for the location of each module solder pad. table 3. module solder pad location figure 6. solder pad reference location solder pad (center of pad) location (x,y) from orign (mm) dimension from orign (mils) 1 (0.30, 4.83) (11.81, 190.16) 2 (0.30, 5.49) (11.81, 216.14) 3 (0.30, 6.15) (11.81, 242.13) 4 (0.30, 6.81) (11.81, 268.11) 5 (0.30, 7.47) (11.81, 294.09) 6 (0.30, 8.13) (11.81, 320.08) 7 (0.30, 8.79) (11.81, 346.06) 8 (0.30, 9.45) (11.81, 372.05) 9 (0.27, 10.11) (10.63, 398.03) 10 (1.21, 10.70) (47.64, 421.26) 11 (1.87, 10.70) (73.62, 421.26) 12 (2.53, 10.70) (99.61, 421.26) 13 (3.19, 10.70) (125.59, 421.26) 14 (3.85, 10.70) (151.57, 421.26) 15 (4.51, 10.70) (177.56, 421.26) 16 (5.17, 10.70) (203.54, 421.26) 17 (5.84, 10.70) (229.92, 421.26) 18 (6.50, 10.70) (255.91, 421.26) 19 (7.16, 10.70) (281.89, 421.26) 20 (7.82, 10.70) (307.87, 421.26) 21 (8.48, 10.70) (333.86, 421.26) 22 (9.14, 10.70) (359.84, 421.26) 23 (9.80, 10.70) (385.83, 421.26) 24 (10.73, 10.11) (422.44, 398.03) 25 (10.70, 9.45) (421.26, 372.05) 26 (10.70, 8.79) (421.26, 346.06) 27 (10.70, 8.13) (421.26, 320.08) 28 (10.70, 7.47) (421.26, 294.09) 29 (10.70, 6.81) ( 421.26, 268.11) 30 (10.70, 6.15) (421.26, 242.13) 31 (10.70, 5.49) (421.26, 216.14) 32 (10.70, 4.83) (421.26, 190.16) top view (seen on host pcb)
preliminary CYBLE-214015-01 document number: 002-15923 rev. *b page 9 of 42 digital and analog capabilities and connections ta b l e 4 and ta b l e 5 detail the solder pad connection definitions and available functions for each connection pad. table 4 lists the solder pads on CYBLE-214015-01, the ble device port-pin, and denotes whether the digital function shown is available for each solder pad. ta b l e 5 denotes whether the analog function shown is available for each solder pad. each connection is configurable for a single option shown with a ? . table 4. digital peripheral capabilities pad number device port pin uart spi i 2 c tcpwm [2,3] capsense wco out eco out lcd swd gpio 1gnd [4] ground connection 2p1.1 ? (scb1_ss1) ? (tcpwm) ??? 3p1.0 ? (tcpwm) ??? 4p1.5 ? (scb0_tx) ? (scb0_miso) ? (scb0_scl) ? (tcpwm) ??? 5p0.1 ? (scb1_tx) ? (scb1_miso) ? (scb1_scl) ? (tcpwm) ??? 6p0.7 ? (scb0_cts) ? (scb0_sclk) ? (tcpwm) ?? ? (swdclk) ? 7 vdd digital power supply input (1.71 v to 5.5 v) 8p1.4 ? (scb0_rx) ? (scb0_mosi) ? (scb0_sda) ? (tcpwm) ??? 9p0.4 ? (scb0_rx) ? (scb0_mosi) ? (scb0_sda) ? (tcpwm) ??? ? 10 p0.5 ? (scb0_tx) ? (scb0_miso) ? (scb0_scl) ? (tcpwm) ??? 11 p0.6 ? (scb0_rts) ? (scb0_ss0) ? (tcpwm) ??? (swdio) ? 12 p1.2 ? (scb1_ss2) ? (tcpwm) ??? 13 v ddr radio power supply (1.9 v to 5.5 v) 14 p2.6 ? (tcpwm) ??? 15 p1.3 ? (scb1_ss3) ? (tcpwm) ??? 16 p3.0 ? (scb0_rx) ? (scb0_sda) ? (tcpwm) ??? 17 p2.1 ? (scb0_ss2) ? (tcpwm) ??? 18 p2.2 ? (scb0_ss3) ? (tcpwm) ??? 19 p2.3 ? (tcpwm) ?? ? ? 20 vdda analog power supply input (1.71 v to 5.5 v) 21 p3.4 ? (scb1_rx) ? (scb1_sda) ? (tcpwm) ??? 22 p3.1 ? (scb0_tx) ? (scb0_scl) ? (tcpwm) ??? 23 p3.7 ? (scb1_cts) ? (tcpwm) ?? ? ? 24 p3.5 ? (scb1_tx) ? (scb1_scl) ? (tcpwm) ??? 25 p3.3 ? (scb0_cts) ? (tcpwm) ??? 26 vref reference voltage input 27 p3.2 ? (scb0_rts) ? (tcpwm) ??? 28 p3.6 ? (scb1_rts) ? (tcpwm) ??? 29 xres external reset hardware connection input 30 p2.4 ? (tcpwm) ??? 31 p2.5 ? (tcpwm) ??? 32 gnd [4] ground connection notes 2. tcpwm stands for timer, counter, and pwm. if supported, t he pad can be configured to any of these peripheral functions. 3. tcpwm connections on ports 0, 1, 2, and 3 can be routed through the digital signal interconnect (dsi) to any of the tcpwm blo cks and can be either positive or negative polarity. 4. the main board needs to connect both gnd connections (pad 1 and pad 32) on the module to the common ground of the system.
preliminary CYBLE-214015-01 document number: 002-15923 rev. *b page 10 of 42 table 5. analog peripheral capabilities pad number device port pin sarmux opamp lpcomp 1gnd [4] ground connection 2p1.1 ? (ctbm1_oa0_inn) 3p1.0 ? (ctbm1_oa0_inp) 4p1.5 ? (ctbm1_oa1_inp) 5p0.1 6p0.7 7 vdd digital power supply input (1.71 to 5.5v) 8p1.4 ? (ctbm1_oa1_inn) 9p0.4 ? (comp1_inp) 10 p0.5 ? (comp1_inn) 11 p0.6 12 p1.2 ? (ctbm1_oa0_out) 13 v ddr radio power supply (1.9v to 5.5v) 14 p2.6 ? (ctbm0_oa0_inp) 15 p1.3 ? (ctbm1_oa1_out) 16 p3.0 ? 17 p2.1 ? (ctbm0_oa0_inn) 18 p2.2 ? (ctbm0_oa0_out) 19 p2.3 ? (ctbm0_oa1_out) 20 vdda analog power supply input (1.71 to 5.5v) 21 p3.4 ? 22 p3.1 ? 23 p3.7 ? 24 p3.5 ? 25 p3.3 ? 26 vref reference voltage input (optional) 27 p3.2 ? 28 p3.6 ? 29 xres external reset hardware connection input 30 p2.4 ? (ctbm0_oa1_inn) 31 p2.5 ? (ctbm0_oa1_inp) 32 gnd ground connection
preliminary CYBLE-214015-01 document number: 002-15923 rev. *b page 11 of 42 power supply connections and re commended external components power connections the CYBLE-214015-01 contains three power supply connec- tions, vdd, vdda, and vddr. the vdd and vdda connections supply power for the digital and analog device operation respec- tively. vddr supplies power for the device radio. vdd and vdda accept a supply range of 1.71 v to 5.5 v. vddr accepts a supply range of 1.9 v to 5.5 v. these specifications can be found in ta b l e 1 0 . the maximum power supply ripple for both power connections on the module is 100 mv, as shown in ta b l e 8 . the power supply ramp rate of vdd and vdda must be equal to or greater than that of vddr when the radio is used. connection options two connection options are available for any application: 1. single supply: connect vdd, vdda, and vddr to the same supply. 2. independent supply: power vdd, vdda, and vddr separately. external component recommendation in either connection scenario, it is recommended to place an external ferrite bead between the supply and the module connection. the ferrite bead should be positioned as close as possible to the module pin connection. figure 7 details the recommended host schematic options for a single supply scenario. the use of one or three ferrite beads will depend on the specific applicat ion and configuration of the CYBLE-214015-01. figure 8 details the recommended host schematic for an independent supply scenario. the recommended ferrite bead value is 330 ? , 100 mhz (murata blm21pg331sn1d). figure 7. recommended host schematic options for single supply option three ferrite bead opti on (seen from bottom) single ferrite bead option (seen from bottom)
preliminary CYBLE-214015-01 document number: 002-15923 rev. *b page 12 of 42 figure 8. recommended host schematic for independent supply option independent power supply option (seen from bottom)
preliminary CYBLE-214015-01 document number: 002-15923 rev. *b page 13 of 42 the CYBLE-214015-01 schematic is shown in figure 9 . figure 9. CYBLE-214015-01 schematic diagram
preliminary CYBLE-214015-01 document number: 002-15923 rev. *b page 14 of 42 critical components list ta b l e 6 details the critical components used in the CYBLE-214015-01 module. table 6. critical component list antenna design ta b l e 7 details antenna used on the CYBLE-214015-01 module. the cypress module performance improves many of these characteristics. for more information, see ta b l e 9 on page 15. table 7. trace antenna specifications component reference designator description silicon u1 76-pin wlcsp programmable system-on-chip (psoc) with ble crystal y1 24.000 mhz, 10pf crystal y2 32.768 khz, 12.5pf item description frequency range 2400?2500 mhz peak gain 0.5-dbi typical average gain ?0.5-dbi typical return loss 10-db minimum
preliminary CYBLE-214015-01 document number: 002-15923 rev. *b page 15 of 42 electrical specifications ta b l e 8 details the absolute maximum electrical characteristics for the cypress ble module. table 8. CYBLE-214015-01 absolute maximum ratings ta b l e 9 details the rf characteristics for the cypress ble module. table 9. CYBLE-214015-01 rf performance characteristics ta b l e 1 0 through table 51 list the module level electrical characteristics for the CYBLE-214015-01. all specifications are valid for ?40 c ? ta ? 85 c and tj ? 100 c, except where noted. specifications ar e valid for 1.71 v to 5.5 v, except where noted. parameter description min typ max unit details/conditions v ddd_abs v dd , v dda or v ddr supply relative to v ss (v ssd = v ssa ) ?0.5 ? 6 v absolute maximum v ccd_abs direct digital core voltage input relative to v ssd ?0.5 ? 1.95 v absolute maximum v ddd_ripple maximum power supply ripple for v dd , v dda and v ddr input voltage ? ? 100 mv 3.0-v supply ripple frequency of 100 khz to 750 khz v gpio_abs gpio voltage ?0.5 ? v dd +0.5 v absolute maximum i gpio_abs maximum current per gpio ?2 5 ? 25 ma absolute maximum i gpio_injection gpio injection curre nt: maximum for v ih > v dd and minimum for v il < v ss ?0.5 ? 0.5 ma absolute maximum current injected per pin lu pin current for latch-up ?200 200 ma ? parameter description min typ max unit details/conditions rf o rf output power on ant ?18 0 3 dbm configurable via register settings rx s rf receive sensitivity on ant ? ?87 ? dbm guaranteed by design simulation f r module frequency range 2400 ? 2480 mhz ? g p peak gain ? 0.5 ? dbi ? g avg average gain ? ?0.5 ? dbi ? rl return loss ? ?10 ? db ? table 10. CYBLE-214015-01 dc specifications parameter description min typ max unit details/conditions v dd1 power supply input voltage (v dd = v dda = v ddr ) 1.71 ? 5.5 v with regulator enabled v dd2 power supply input voltage unregulated (v dd = v dda = v ddr ) 1.71 1.8 1.89 v internally unregulated supply v ddr1 radio supply voltage (radio on) 1.9 ? 5.5 v ? v ddr2 radio supply voltage (radio off) 1.71 ? 5.5 v ? active mode, v dd = 1.71 v to 5.5 v i dd3 execute from flash; cpu at 3 mhz ? 1.7 ? ma t = 25 c, v dd = 3.3 v i dd4 execute from flash; cpu at 3 mhz ? ? ? ma t = ?40 c to 85 c i dd5 execute from flash; cpu at 6 mhz ? 2.5 ? ma t = 25 c, v dd = 3.3 v i dd6 execute from flash; cpu at 6 mhz ? ? ? ma t = ?40 c to 85 c i dd7 execute from flash; cpu at 12 mhz ? 4 ? ma t = 25 c, v dd = 3.3 v
preliminary CYBLE-214015-01 document number: 002-15923 rev. *b page 16 of 42 i dd8 execute from flash; cpu at 12 mhz ? ? ? ma t = ?40 c to 85 c i dd9 execute from flash; cpu at 24 mhz ? 7.1 ? ma t = 25 c, v dd = 3.3v i dd10 execute from flash; cpu at 24 mhz ? ? ? ma t = ?40 c to 85 c i dd11 execute from flash; cpu at 48 mhz ? 13.4 ? ma t = 25 c, v dd = 3.3v i dd12 execute from flash; cpu at 48 mhz ? ? ? ma t = ?40 c to 85 c sleep mode, v dd = 1.71 v to 5.5 v i dd13 imo on ? ? ? ma t = 25 c, v dd = 3.3v, sysclk = 3 mhz sleep mode, v dd and v ddr = 1.9v to 5.5v i dd14 eco on ? ? ? ma t = 25 c, v dd = 3.3v, sysclk = 3 mhz deep-sleep mode, v dd = 1.71 v to 3.6 v i dd15 wdt with wco on ? 1.3 ? a t = 25 c, v dd = 3.3v i dd16 wdt with wco on ? ? ? a t = ?40 c to 85 c i dd17 wdt with wco on ? ? ? a t = 25 c, v dd = 5v i dd18 wdt with wco on ? ? ? a t = ?40 c to 85 c deep-sleep mode, v dd = 1.71 v to 1.89 v (regulator bypassed) i dd19 wdt with wco on ? ? ? a t = 25 c i dd20 wdt with wco on ? ? ? a t = ?40 c to 85 c hibernate mode, v dd = 1.71 v to 3.6 v i dd27 gpio and reset active ? 150 ? na t = 25 c, v dd = 3.3v i dd28 gpio and reset active ? ? ? na t = ?40 c to 85 c hibernate mode, v dd = 3.6 v to 5.5 v i dd29 gpio and reset active ? ? ? na t = 25 c, v dd = 5v i dd30 gpio and reset active ? ? ? na t = ?40 c to 85 c stop mode, v dd = 1.71 v to 3.6 v i dd33 stop-mode current (v dd )?20?na t = 25 c, v dd = 3.3v i dd34 stop-mode current (v ddr ) ? 40 ?- na t = 25 c, v ddr = 3.3v i dd35 stop-mode current (v dd ) ? ? ? na t = ?40 c to 85 c i dd36 stop-mode current (v ddr )???na t = ?40 c to 85 c, v ddr = 1.9 v to 3.6v stop mode, v dd = 3.6 v to 5.5 v i dd37 stop-mode current (v dd )???na t = 25 c, v dd = 5v i dd38 stop-mode current (v ddr )???na t = 25 c, v ddr = 5v i dd39 stop-mode current (v dd ) ? ? ? na t = ?40 c to 85 c i dd40 stop-mode current (v ddr ) ? ? ? na t = ?40 c to 85 c table 10. CYBLE-214015-01 dc specifications (continued) parameter description min typ max unit details/conditions
preliminary CYBLE-214015-01 document number: 002-15923 rev. *b page 17 of 42 table 11. ac specifications gpio parameter description min typ max unit details/conditions f cpu cpu frequency dc ? 48 mhz 1.71 v ?? v dd ?? 5.5 v t sleep wakeup from sleep mode ? 0 ? s guaranteed by characterization t deepsleep wakeup from deep-sleep mode ? ? 25 s 24-mhz imo. guaranteed by characterization t hibernate wakeup from hibernate mode ? ? 800 s guaranteed by characterization t stop wakeup from stop mode ? ? 2 ms xres wakeup table 12. gpio dc specifications parameter description min typ max unit details/conditions v ih [5] input voltage high threshold 0.7 v dd ? ? v cmos input lvttl input, v dd < 2.7 v 0.7 v dd ? ? v ? lvttl input, v dd ? 2.7 v 2.0 ? ? v ? v il input voltage low threshold ? ? 0.3 v dd vcmos input lvttl input, v dd < 2.7 v ? ? 0.3 v dd v? lvttl input, v dd ? 2.7 v ? ? 0.8 v ? v oh output voltage high level v dd ? 0.6 ? ? v i oh = 4 ma at 3.3-v v dd output voltage high level v dd ? 0.5 ? ? v i oh = 1 ma at 1.8-v v dd v ol output voltage low level ? ? 0.6 v i ol = 8 ma at 3.3-v v dd output voltage low level ? ? 0.6 v i ol = 4 ma at 1.8-v v dd output voltage low level ? ? 0.4 v i ol = 3 ma at 3.3-v v dd r pullup pull-up resistor 3.5 5.6 8.5 k ? ? r pulldown pull-down resistor 3.5 5.6 8.5 k ? ? i il input leakage current (absolute value) ? ? 2 na 25 c, v dd = 3.3v i il_ctbm input leakage on ctbm input pins ? ? 4 na ? c in input capacitance ? ? 7 pf ? v hysttl input hysteresis lvttl 25 40 ? mv v dd > 2.7v v hyscmos input hysteresis cmos 0.05 v dd ? ? 1 ? i diode current through protection diode to v dd /v ss ? ? 100 a ? i tot_gpio maximum total source or sink chip current ? ? 200 ma ? note 5. v ih must not exceed v dd + 0.2 v.
preliminary CYBLE-214015-01 document number: 002-15923 rev. *b page 18 of 42 table 13. gpio ac specifications xres analog peripherals opamp parameter description min typ max unit details/conditions t risef rise time in fast-strong mode 2 ? 12 ns 3.3-v v ddd , c load = 25 pf t fallf fall time in fast-strong mode 2 ? 12 ns 3.3-v v ddd , c load = 25 pf t rises rise time in slow-strong mode 10 ? 60 ns 3.3-v v ddd , c load = 25 pf t falls fall time in slow-strong mode 10 ? 60 ns 3.3-v v ddd , c load = 25 pf f gpiout1 gpio fout; 3.3 v ? v dd ?? 5.5 v fast-strong mode ??33mhz 90/10%, 25-pf load, 60/40 duty cycle f gpiout2 gpio fout; 1.7 v ?? v dd ?? 3.3 v fast-strong mode ? ? 16.7 mhz 90/10%, 25-pf load, 60/40 duty cycle f gpiout3 gpio fout; 3.3 v ?? v dd ?? 5.5 v slow-strong mode ?? 7 mhz 90/10%, 25-pf load, 60/40 duty cycle f gpiout4 gpio fout; 1.7 v ?? v dd ?? 3.3 v slow-strong mode ??3.5mhz 90/10%, 25-pf load, 60/40 duty cycle f gpioin gpio input operating frequency 1.71 v ?? v dd ?? 5.5 v ? ? 48 mhz 90/10% v io table 14. xres dc specifications parameter description min typ max unit details/conditions v ih input voltage high threshold 0.7 v ddd ? ? v cmos input v il input voltage low threshold ? ? 0.3 v ddd v cmos input r pullup pull-up resistor 3.5 5.6 8.5 k ? ? c in input capacitance ? 3 ? pf ? v hysxres input voltage hysteresis ? 100 ? mv ? i diode current through protection diode to v dd /v ss ? ? 100 a ? table 15. xres ac specifications parameter description min typ max unit details/conditions t resetwidth reset pulse width 1 ? ? s ? table 16. opamp specifications parameter description min typ max unit details/conditions i dd (opamp block current. v dd = 1.8 v. no load) i dd_hi power = high ? 1000 1300 a ? i dd_med power = medium ? 500 ? a ? i dd_low power = low ? 250 350 a ? gbw (load = 20 pf, 0.1 ma. v dda = 2.7 v) gbw_hi power = high 6 ? ? mhz ? gbw_med power = medium 4 ? ? mhz ? gbw_lo power = low ? 1 ? mhz ? i out_max (v dda ? 2.7 v, 500 mv from rail) i out_max_hi power = high 10 ? ? ma ?
preliminary CYBLE-214015-01 document number: 002-15923 rev. *b page 19 of 42 i out_max_mid power = medium 10 ? ? ma ? i out_max_lo power = low ? 5 ? ma ? i out (v dda = 1.71 v, 500 mv from rail) i out_max_hi power = high 4 ? ? ma ? i out_max_mid power = medium 4 ? ? ma ? i out_max_lo power = low ? 2 ? ma ? v in charge pump on, v dda ? 2.7 v ?0.05 ? v dda ? 0.2 v ? v cm charge pump on, v dda ? 2.7 v ?0.05 ? v dda ? 0.2 v ? v out (v dda ? 2.7 v) v out_1 power = high, i load = 10 ma 0.5 ? v dda ? 0.5 v ? v out_2 power = high, i load = 1 ma 0.2 ? v dda ? 0.2 v ? v out_3 power = medium, i load = 1 ma 0.2 ? v dda ? 0.2 v ? v out_4 power = low, i load = 0.1 ma 0.2 ? v dda ? 0.2 v ? v os_tr offset voltage, trimmed 1 0.5 1 mv high mode v os_tr offset voltage, trimmed ? 1 ? mv medium mode v os_tr offset voltage, trimmed ? 2 ? mv low mode v os_dr_tr offset voltage drift, trimmed ?10 3 10 v/c high mode v os_dr_tr offset voltage drift, trimmed ? 10 ? v/c medium mode v os_dr_tr offset voltage drift, trimmed ? 10 ? v/c low mode cmrr dc 65 70 ? db v ddd = 3.6v, high-power mode psrr at 1 khz, 100-mv ripple 70 85 ? db v ddd = 3.6v noise v n1 input referred, 1 hz?1 ghz, power = high ? 94 ? vrms ? v n2 input referred, 1 khz, power = high ? 72 ? nv/rthz ? v n3 input referred, 10 khz, power = high ? 28 ? nv/rthz ? v n4 input referred, 100 khz, power = high ? 15 ? nv/rthz ? c load stable up to maximum load. perfor- mance specs at 50 pf ??125pf ? slew_rate cload = 50 pf, power = high, v dda ? 2.7 v 6? ? v/s ? t_op_wake from disable to enable, no external rc dominating ?300 ? s ? comp_mode (comparator mode; 50-mv drive, t rise = t fall (approx.) t pd1 response time; power = high ? 150 ? ns ? t pd2 response time; power = medium ? 400 ? ns ? t pd3 response time; power = low ? 2000 ? ns ? vhyst_op hysteresis ? 10 ? mv ? deep-sleep mode (deep-sleep mode operation is only guaranteed for v dda > 2.5v) gbw_ds gain bandwidth product ? 50 ? khz ? idd_ds current ? 15 ? a ? vos_ds offset voltage ? 5 ? mv ? vos_dr_ds offset voltage drift ? 20 ? v/c ? vout_ds output voltage 0.2 ? v dd ?0.2 v ? vcm_ds common mode voltage 0.2 ? v dd ? 1.8 v ? table 16. opamp specifications (continued) parameter description min typ max unit details/conditions
preliminary CYBLE-214015-01 document number: 002-15923 rev. *b page 20 of 42 temperature sensor sar adc table 17. comparator dc specifications parameter description min typ max unit details/conditions v offset1 input offset voltage, factory trim ? ? 10 mv ? v offset2 input offset voltage, custom trim ? ? 6 mv ? v offset3 input offset voltage, ultra-low-power mode ? 12 ? mv ? v hyst hysteresis when enabled ? 10 35 mv ? v icm1 input common mode voltage in normal mode 0 ? v ddd ? 0.1 v modes 1 and 2 v icm2 input common mode voltage in low-power mode 0? v ddd v? v icm3 input common mode voltage in ultra low-power mode 0?v ddd ? 1.15 v ? cmrr common mode rejection ratio 50 ? ? db v ddd ? 2.7 v cmrr common mode rejection ratio 42 ? ? db v ddd ? 2.7 v i cmp1 block current, normal mode ? ? 400 a ? i cmp2 block current, low-power mode ? ? 100 a ? i cmp3 block current in ultra-low-power mode ? 6 ? a ? z cmp dc input impedance of comparator 35 ? ? m ? ? table 18. comparator ac specifications parameter description min typ max unit details/conditions t resp1 response time, normal mode, 50-mv overdrive ? 38 ? ns 50-mv overdrive t resp2 response time, low-power mode, 50-mv overdrive ? 70 ? ns 50-mv overdrive t resp3 response time, ultra-low-power mode, 50-mv overdrive ? 2.3 ? s 200-mv overdrive table 19. temperature sensor specifications parameter description min typ max unit details/conditions t sensacc temperature-sensor accuracy ?5 1 5 c ?40 to +85 c table 20. sar adc dc specifications parameter description min typ max unit details/conditions a_res resolution ? ? 12 bits ? a_chnis_s number of channels - single-ended ? ? 8 ? 8 full-speed a-chnks_d number of channels - differential ? ? 4 ? diff inputs use neighboring i/o a-mono monotonicity ? ? ? ? yes a_gainerr gain error ? ? 0.1 % with external reference a_offset input offset voltage ? ? 2 mv measured with 1-v v ref a_isar current consumption ? ? 1 ma ? a_vins input voltage range - single-ended v ss ?v dda v? a_vind input voltage range - differential v ss ? v dda v? a_inres input resistance ? ? 2.2 k ? ?
preliminary CYBLE-214015-01 document number: 002-15923 rev. *b page 21 of 42 csd a_incap input capacitance ? ? 10 pf ? vrefsar trimmed internal reference to sar ?1 ? 1 % percentage of vbg (1.024 v) table 20. sar adc dc specifications (continued) parameter description min typ max unit details/conditions table 21. sar adc ac specifications parameter description min typ max unit details/conditions a_psrr power-supply rejection ratio 70 ? ? db measured at 1-v reference a_cmrr common-mode rejection ratio 66 ? ? db ? a_samp sample rate ? ? 1 msps ? fsarintref sar operating speed without external ref. bypass ? ? 100 ksps 12-bit resolution a_snr signal-to-noise ratio (snr) 65 ? ? db f in = 10 khz a_bw input bandwidth without aliasing ? ? a_samp/2 khz ? a_inl integral nonlinearity. v dd = 1.71 v to 5.5 v, 1 msps ?1.7 ? 2 lsb v ref = 1 v to v dd a_inl integral nonlinearity. v ddd = 1.71 v to 3.6 v, 1 msps ?1.5 ? 1.7 lsb v ref = 1.71 v to v dd a_inl integral nonlinearity. v dd = 1.71 v to 5.5 v, 500 ksps ?1.5 ? 1.7 lsb v ref = 1 v to v dd a_dnl differential nonlinearity. v dd = 1.71 v to 5.5 v, 1 msps ?1 ? 2.2 lsb v ref = 1 v to v dd a_dnl differential nonlinearity. v dd = 1.71 v to 3.6 v, 1 msps ?1 ? 2 lsb v ref = 1.71 v to v dd a_dnl differential nonlinearity. v dd = 1.71 v to 5.5 v, 500 ksps ?1 ? 2.2 lsb v ref = 1 v to v dd a_thd total harmonic distortion ? ? ?65 db f in = 10 khz table 22. csd block specifications parameter description min typ max unit details/conditions v csd voltage range of operation 1.71 ? 5.5 v ? idac1 dnl for 8-bit resolution ?1 ? 1 lsb ? idac1 inl for 8-bit resolution ?3 ? 3 lsb ? idac2 dnl for 7-bit resolution ?1 ? 1 lsb ? idac2 inl for 7-bit resolution ?3 ? 3 lsb ? snr ratio of counts of finger to noise 5 ? ? ratio capacitance range of 9 pf to 35 pf, 0.1-pf sensitivity. radio is not operating during the scan i dac1_crt1 output current of idac1 (8 bits) in high range ? 612 ? a ? i dac1_crt2 output current of idac1 (8 bits) in low range ? 306 ? a ? i dac2_crt1 output current of idac2 (7 bits) in high range ? 305 ? a ? i dac2_crt2 output current of idac2 (7 bits) in low range ? 153 ? a ?
preliminary CYBLE-214015-01 document number: 002-15923 rev. *b page 22 of 42 digital peripherals timer counter pulse width modulation (pwm) table 23. timer dc specifications parameter description min typ max unit details/conditions i tim1 block current consumption at 3 mhz ? ? 42 a 16-bit timer i tim2 block current consumption at 12 mhz ? ? 130 a 16-bit timer i tim3 block current consumption at 48 mhz ? ? 535 a 16-bit timer table 24. timer ac specifications parameter description min typ max unit details/conditions t timfreq operating frequency f clk ?48mhz ? t capwint capture pulse width (internal) 2 t clk ??ns ? t capwext capture pulse width (external) 2 t clk ??ns ? t timres timer resolution t clk ??ns ? t tenwidint enable pulse width (internal) 2 t clk ??ns ? t tenwidext enable pulse width (external) 2 t clk ??ns ? t timreswint reset pulse width (internal) 2 t clk ??ns ? t timresext reset pulse width (external) 2 t clk ??ns ? table 25. counter dc specifications parameter description min typ max unit details/conditions i ctr1 block current consumption at 3 mhz ? ? 42 a 16-bit counter i ctr2 block current consumption at 12 mhz ? ? 130 a 16-bit counter i ctr3 block current consumption at 48 mhz ? ? 535 a 16-bit counter table 26. counter ac specifications parameter description min typ max unit details/conditions t ctrfreq operating frequency f clk ?48mhz ? t ctrpwint capture pulse width (internal) 2 t clk ??ns ? t ctrpwext capture pulse width (external) 2 t clk ??ns ? t ctres counter resolution t clk ??ns ? t cenwidint enable pulse width (internal) 2 t clk ??ns ? t cenwidext enable pulse width (external) 2 t clk ??ns ? t ctrreswint reset pulse width (internal) 2 t clk ??ns ? t ctrreswext reset pulse width (external) 2 t clk ?? ns ? table 27. pwm dc specifications parameter description min typ max unit details/conditions i pwm1 block current consumption at 3 mhz ? ? 42 a 16-bit pwm i pwm2 block current consumption at 12 mhz ? ? 130 a 16-bit pwm i pwm3 block current consumption at 48 mhz ? ? 535 a 16-bit pwm
preliminary CYBLE-214015-01 document number: 002-15923 rev. *b page 23 of 42 lcd direct drive table 28. pwm ac specifications parameter description min typ max unit details/conditions t pwmfreq operating frequency f clk ?48mhz ? t pwmpwint pulse width (internal) 2 t clk ??ns ? t pwmext pulse width (external) 2 t clk ??ns ? t pwmkillint kill pulse width (internal) 2 t clk ??ns ? t pwmkillext kill pulse width (external) 2 t clk ??ns ? t pwmeint enable pulse width (internal) 2 t clk ??ns ? t pwmenext enable pulse width (external) 2 t clk ??ns ? t pwmreswint reset pulse width (internal) 2 t clk ??ns ? t pwmreswext reset pulse width (external) 2 t clk ??ns ? table 29. lcd direct drive dc specifications spec id parameter description min typ max unit details/conditions sid228 i lcdlow operating current in low-power mode ? 17.5 ? a 16 4 small segment display at 50 hz sid229 c lcdcap lcd capacitance per segment/common driver ? 500 5000 pf ? sid230 lcd offset long-term segment offset ? 20 ? mv ? sid231 i lcdop1 lcd system operating current v bias = 5 v ?2?ma 32 4 segments. 50 hz at 25 c sid232 i lcdop2 lcd system operating current v bias = 3.3 v ?2?ma 32 4 segments 50 hz at 25 c table 30. lcd direct drive ac specifications spec id parameter description min typ max unit details/conditions sid233 f lcd lcd frame rate 10 50 150 hz ?
preliminary CYBLE-214015-01 document number: 002-15923 rev. *b page 24 of 42 serial communication table 33. fixed uart dc specifications table 34. fixed uart ac specifications table 31. fixed i 2 c dc specifications parameter description min typ max unit details/conditions i i2c1 block current consumption at 100 khz ? ? 50 a ? i i2c2 block current consumption at 400 khz ? ? 155 a ? i i2c3 block current consumption at 1 mbps ? ? 390 a ? i i2c4 i 2 c enabled in deep-sleep mode ? ? 1.4 a ? table 32. fixed i 2 c ac specifications parameter description min typ max unit details/conditions f i2c1 bit rate ? ? 400 khz ? parameter description min typ max unit details/conditions i uart1 block current consumption at 100 kbps ? ? 55 a ? i uart2 block current consumption at 1000 kbps ? ? 312 a ? parameter description min typ max unit details/conditions f uart bit rate ? ? 1 mbps ? table 35. fixed spi dc specifications parameter description min typ max unit details/conditions i spi1 block current consumption at 1 mbps ? ? 360 a ? i spi2 block current consumption at 4 mbps ? ? 560 a ? i spi3 block current consumption at 8 mbps ? ? 600 a ? table 36. fixed spi ac specifications parameter description min typ max unit details/conditions f spi spi operating frequency (master; 6x over sampling) ? ? 8 mhz ? table 37. fixed spi master mode ac specifications parameter description min typ max unit details/conditions t dmo mosi valid after sclk driving edge ? ? 18 ns ? t dsi miso valid before sclk capturing edge full clock, late miso sampling used 20 ? ? ns full clock, late miso sampling t hmo previous mosi data hold time 0 ? ? ns referred to slave capturing edge table 38. fixed spi slave mode ac specifications parameter description min typ max unit details/conditions t dmi mosi valid before sclk capturing edge 40 ? ? ns t dso miso valid after sclk driving edge ? ? 42 + 3 t cpu ns t dso_ext miso valid after sclk driving edge in external clock mode. v dd < 3.0v ? ? 50 ns t hso previous miso data hold time 0 ? ? ns t sselsck ssel valid to first sc k valid edge 100 ? ? ns
preliminary CYBLE-214015-01 document number: 002-15923 rev. *b page 25 of 42 memory system resources power-on-reset (por) note 6. it can take as much as 20 ms to write to flash. during this time, the device should not be reset, or flash operations will be interrupted and cannot be relied on to have completed. reset sources include the xres pin, software resets , cpu lockup states and privilege violations, improper power supp ly levels, and watchdogs. make certain that these are not inadvertently activated. table 39. flash dc specifications parameter description min typ max unit details/conditions v pe erase and program voltage 1.71 ? 5.5 v ? t ws48 number of wait states at 32?48 mhz 2 ? ? ? cpu execution from flash t ws32 number of wait states at 16?32 mhz 1 ? ? ? cpu execution from flash t ws16 number of wait states for 0?16 mhz 0 ? ? ? cpu execution from flash table 40. flash ac specifications parameter description min typ max unit details/conditions t rowwrite [6] row (block) write time (erase and program) ? ? 20 ms row (block) = 256 bytes t rowerase [6] row erase time ? ? 13 ms ? t rowprogram [6] row program time after erase ? ? 7 ms ? t bulkerase [6] bulk erase time (256 kb) ? ? 35 ms ? t devprog [6] total device program time ? ? 25 seconds ? f end flash endurance 100 k ? ? cycles ? f ret flash retention. t a ? 55 c, 100 k p/e cycles. 20 ? ? years ? f ret2 flash retention. t a ? 85 c, 10 k p/e cycles. 10 ? ? years ? table 41. por dc specifications parameter description min typ max unit details/conditions v riseipor rising trip voltage 0.80 ? 1.45 v ? v fallipor falling trip voltage 0.75 ? 1.40 v ? v iporhyst hysteresis 15 ? 200 mv ? table 42. por ac specifications parameter description min typ max unit details/conditions t ppor_tr precision power-on reset (ppor) response time in active and sleep modes ??1s ? table 43. brown-out detect parameter description min typ max unit details/conditions v fallppor bod trip voltage in active and sleep modes 1.64 ? ? v ? v falldpslp bod trip voltage in deep sleep 1.4 ? ? v ? table 44. hibernate reset parameter description min typ max unit details/conditions v hbrtrip bod trip voltage in hibernate 1.1 ? ? v ?
preliminary CYBLE-214015-01 document number: 002-15923 rev. *b page 26 of 42 voltage monitors (lvd) swd interface table 45. voltage monitor dc specifications parameter description min typ max unit details/conditions v lvi1 lvi_a/d_sel[3:0] = 0000b 1.71 1.75 1.79 v ? v lvi2 lvi_a/d_sel[3:0] = 0001b 1.76 1.80 1.85 v ? v lvi3 lvi_a/d_sel[3:0] = 0010b 1.85 1.90 1.95 v ? v lvi4 lvi_a/d_sel[3:0] = 0011b 1.95 2.00 2.05 v ? v lvi5 lvi_a/d_sel[3:0] = 0100b 2.05 2.10 2.15 v ? v lvi6 lvi_a/d_sel[3:0] = 0101b 2.15 2.20 2.26 v ? v lvi7 lvi_a/d_sel[3:0] = 0110b 2.24 2.30 2.36 v ? v lvi8 lvi_a/d_sel[3:0] = 0111b 2.34 2.40 2.46 v ? v lvi9 lvi_a/d_sel[3:0] = 1000b 2.44 2.50 2.56 v ? v lvi10 lvi_a/d_sel[3:0] = 1001b 2.54 2.60 2.67 v ? v lvi11 lvi_a/d_sel[3:0] = 1010b 2.63 2.70 2.77 v ? v lvi12 lvi_a/d_sel[3:0] = 1011b 2.73 2.80 2.87 v ? v lvi13 lvi_a/d_sel[3:0] = 1100b 2.83 2.90 2.97 v ? v lvi14 lvi_a/d_sel[3:0] = 1101b 2.93 3.00 3.08 v ? v lvi15 lvi_a/d_sel[3:0] = 1110b 3.12 3.20 3.28 v ? v lvi16 lvi_a/d_sel[3:0] = 1111b 4.39 4.50 4.61 v ? lvi_idd block current ? ? 100 a ? table 46. voltage monitor ac specifications parameter description min typ max unit details/conditions t montrip voltage monitor trip time ? ? 1 s ? table 47. swd interface specifications parameter description min typ max unit details/conditions f_swdclk1 3.3 v ? v dd ? 5.5 v ? ? 14 mhz swdclk ?? 1/3 cpu clock frequency f_swdclk2 1.71 v ? v dd ? 3.3 v ? ? 7 mhz swdclk ?? 1/3 cpu clock frequency t_swdi_setup t = 1/f swdclk 0.25 t ? ? ns ? t_swdi_hold t = 1/f swdclk 0.25 t ? ? ns ? t_swdo_valid t = 1/f swdclk ? ? 0.5 t ns ? t_swdo_hold t = 1/f swdclk 1 ? ? ns ?
preliminary CYBLE-214015-01 document number: 002-15923 rev. *b page 27 of 42 internal main oscillator internal low-speed oscillator table 52. recommended eco trim value table 48. imo dc specifications parameter description min typ max unit details/conditions i imo1 imo operating current at 48 mhz ? ? 1000 a ? i imo2 imo operating current at 24 mhz ? ? 325 a ? i imo3 imo operating current at 12 mhz ? ? 225 a ? i imo4 imo operating current at 6 mhz ? ? 180 a ? i imo5 imo operating current at 3 mhz ? ? 150 a ? table 49. imo ac specifications parameter description min typ max unit details/conditions f imotol3 frequency variation from 3 to 48 mhz ? ? 2 % with api-called calibration f imotol3 imo startup time ? 12 ? s ? table 50. ilo dc specifications parameter description min typ max unit details/conditions i ilo2 ilo operating current at 32 khz ? 0.3 1.05 a ? table 51. ilo ac specifications parameter description min typ max unit details/conditions t startilo1 ilo startup time ? ? 2 ms ? f ilotrim1 32-khz trimmed frequency 15 32 50 khz ? parameter description value details/conditions eco trim 24-mhz trim value (firmware configuration) 0x00009595 recommended trim value that needs to be loaded to register cy_sys_xtal_blerd_bb_xo_captrim_reg table 53. udb ac specifications parameter description min typ max unit details/conditions data path performance f max-timer max frequency of 16-bit timer in a udb pair ??48mhz ? f max-adder max frequency of 16-bit adder in a udb pair ??48mhz ? f max_crc max frequency of 16-bit crc/prs in a udb pair ??48mhz ? pld performance in udb f max_pld max frequency of 2-pass pld function in a udb pair ??48mhz ? clock to output performance t clk_out_udb1 prop. delay for clock in to data out at 25 c, typical ?15 ? ns ? t clk_out_udb2 prop. delay for clock in to data out, worst case ?25 ? ns ?
preliminary CYBLE-214015-01 document number: 002-15923 rev. *b page 28 of 42 table 54. ble subsystem parameter description min typ max unit details/conditions rf receiver specification rxs, idle rx sensitivity with idle transmitter ? ?89 ? dbm ? rx sensitivity with idle transmitter excluding balun loss ? ?91 ? dbm guaranteed by design simulation rxs, dirty rx sensitivity with dirty transmitter ? ?87 ?70 dbm rf-phy specification (rcv-le/ca/01/c) rxs, highgain rx sensitivity in high-gain mode with idle transmitter ? ?91 ? dbm ? prxmax maximum input power ?10 ?1 ? dbm rf-phy specification (rcv-le/ca/06/c) ci1 cochannel interference, wanted signal at ?67 dbm and inter- ferer at frx ?9 21 db rf-phy specification (rcv-le/ca/03/c) ci2 adjacent channel interference wanted signal at ?67 dbm and inter- ferer at frx 1 mhz ?3 15 db rf-phy specification (rcv-le/ca/03/c) ci3 adjacent channel interference wanted signal at ?67 dbm and inter- ferer at frx 2 mhz ? ?29 ? db rf-phy specification (rcv-le/ca/03/c) ci4 adjacent channel interference wanted signal at ?67 dbm and inter- ferer at ? frx 3 mhz ? ?39 ? db rf-phy specification (rcv-le/ca/03/c) ci5 adjacent channel interference wanted signal at ?67 dbm and inter- ferer at image frequency (f image ) ? ?20 ? db rf-phy specification (rcv-le/ca/03/c) ci3 adjacent channel interference wanted signal at ?67 dbm and inter- ferer at image frequency (f image 1mhz) ? ?30 ? db rf-phy specification (rcv-le/ca/03/c) obb1 out-of-band blocking, wanted signal at ?67 dbm and inter- ferer at f = 30?2000 mhz ?30 ?27 ? dbm rf-phy specification (rcv-le/ca/04/c) obb2 out-of-band blocking, wanted signal at ?67 dbm and inter- ferer at f = 2003?2399 mhz ?35 ?27 ? dbm rf-phy specification (rcv-le/ca/04/c) obb3 out-of-band blocking, wanted signal at ?67 dbm and inter- ferer at f = 2484?2997 mhz ?35 ?27 ? dbm rf-phy specification (rcv-le/ca/04/c) obb4 out-of-band blocking, wanted signal a ?67 dbm and inter- ferer at f = 3000?12750 mhz ?30 ?27 ? dbm rf-phy specification (rcv-le/ca/04/c) imd intermodulation performance wanted signal at ?64 dbm and 1-mbps ble, third, fourth, and fifth offset channel ?50 ? ? dbm rf-phy specification (rcv-le/ca/05/c) rxse1 receiver spurious emission 30 mhz to 1.0 ghz ???57dbm 100-khz measurement bandwidth etsi en300 328 v1.8.1
preliminary CYBLE-214015-01 document number: 002-15923 rev. *b page 29 of 42 rxse2 receiver spurious emission 1.0 ghz to 12.75 ghz ???47dbm 1-mhz measurement bandwidth etsi en300 328 v1.8.1 rf transmitter specifications txp, acc rf power accuracy ? 1 ? db ? txp, range rf power control range ? 20 ? db ? txp, 0dbm output power, 0-db gain setting (pa7) ?0 ? dbm ? txp, max output power, maximum power setting (pa10) ?3 ? dbm ? txp, min output power, minimum power setting (pa1) ? ?18 ? dbm ? f2avg average frequency deviation for 10101010 pattern 185 ? ? khz rf-phy specification (trm-le/ca/05/c) f1avg average frequency deviation for 11110000 pattern 225 250 275 khz rf-phy specification (trm-le/ca/05/c) eo eye opening = ? f2avg/ ? f1avg 0.8 ? ? rf-phy specification (trm-le/ca/05/c) ftx, acc frequency accuracy ?150 ? 150 khz rf-phy specification (trm-le/ca/06/c) ftx, maxdr maximum frequency drift ?50 ? 50 khz rf-phy specification (trm-le/ca/06/c) ftx, initdr initial frequency drift ?20 ? 20 khz rf-phy specification (trm-le/ca/06/c) ftx, dr maximum drift rate ?20 ? 20 khz/ 50 s rf-phy specification (trm-le/ca/06/c) ibse1 in-band spurious emission at 2-mhz offset ???20dbm rf-phy specification (trm-le/ca/03/c) ibse2 in-band spurious emission at ? 3-mhz offset ???30dbm rf-phy specification (trm-le/ca/03/c) txse1 transmitter spurious emissions (average), <1.0 ghz ? ? ?55.5 dbm fcc-15.247 txse2 transmitter spurious emissions (average), >1.0 ghz ? ? ?41.5 dbm fcc-15.247 rf current specifications irx receive current in normal mode ? 18.7 ? ma ? irx_rf radio receive current in normal mode ? 16.4 ? ma measured at v ddr irx, highgain receive current in high-gain mode ? 21.5 ? ma ? itx, 3dbm tx current at 3-dbm setting (pa10) ? 20 ? ma ? itx, 0dbm tx current at 0-dbm setting (pa7) ? 16.5 ? ma ? itx_rf, 0dbm radio tx current at 0 dbm setting (pa7) ? 15.6 ? ma measured at v ddr itx_rf, 0dbm radio tx current at 0 dbm excluding balun loss ?14.2 ? ma guaranteed by design simulation itx,-3dbm tx current at ?3-dbm setting (pa4) ? 15.5 ? ma ? itx,-6dbm tx current at ?6-dbm setting (pa3) ? 14.5 ? ma ? table 54. ble subsystem (continued) parameter description min typ max unit details/conditions
preliminary CYBLE-214015-01 document number: 002-15923 rev. *b page 30 of 42 itx,-12dbm tx current at ?12-dbm setting (pa2) ? 13.2 ? ma ? itx,-18dbm tx current at ?18-dbm setting (pa1) ? 12.5 ? ma ? iavg_1sec, 0dbm average current at 1-second ble connection interval ?17.1 ? a txp: 0 dbm; 20-ppm master and slave clock accuracy. for empty pdu exchange. iavg_4sec, 0dbm average current at 4-second ble connection interval ?6.1 ? a txp: 0 dbm; 20-ppm master and slave clock accuracy. for empty pdu exchange. general rf specifications freq rf operating frequency 2400 ? 2482 mhz ? chbw channel spacing ? 2 ? mhz ? dr on-air data rate ? 1000 ? kbps ? idle2tx ble.idle to ble. tx transition time ? 120 140 s ? idle2rx ble.idle to ble. rx transition time ? 75 120 s ? rssi specifications rssi, acc rssi accuracy ? 5 ? db ? rssi, res rssi resolution ? 1 ? db ? rssi, per rssi sample period ? 6 ? s ? table 54. ble subsystem (continued) parameter description min typ max unit details/conditions
preliminary CYBLE-214015-01 document number: 002-15923 rev. *b page 31 of 42 environmental specifications environmental compliance this cypress ble module is built in comp liance with the restriction of hazardous su bstances (rohs) and halogen free (hf) directives. the cypress module and components used to produce this module are rohs and hf compliant. rf certification the CYBLE-214015-01 module is certified under the following rf certification standards: fcc id: wap4008 ce ic: 7922a-4008 mic: 203-jn0505 kc: msip-crm-cyp-4008 environmental conditions ta b l e 5 5 describes the operating and storage conditions for the cypress ble module. table 55. environmental conditions for CYBLE-214015-01 esd and emi protection exposed components require special attention to esd and electromagnetic interference (emi). a grounded conductive layer inside the device enclosure is sugge sted for emi and esd performance. any openings in the enclosure near the module should be surrounded by a grounded conductive la yer to provide esd protection and a low-impedance path to groun d. device handling : proper esd protocol must be followed in manu facturing to ensure component reliability. description minimum specification maximum specification operating temperature ?40 c 85 c operating humidity (relative, non-condensation) 5% 85% thermal ramp rate ? 3 c/minute storage temperature ?40 c 85 c storage temperature and humidity ? 85 c at 85% esd: module integrated into system components [7] ? 15 kv air 2.2 kv contact note 7. this does not apply to the rf pins (ant, xtali, and xtalo). rf pins (ant, xtali, and xtalo) are tested for 500-v hbm.
preliminary CYBLE-214015-01 document number: 002-15923 rev. *b page 32 of 42 regulatory information fcc fcc notice: the device CYBLE-214015-01 complies with part 15 of the fcc rules. the device meets the requirements for modular transmitter approval as detailed in fcc public notice da00-1407. transmitter operation is subject to the following two conditions: (1) this device may not cause harmful interference, and (2) this device must a ccept any interference received, including interference that may cause undesired operation. caution: the fcc requires the user to be notified that any changes or m odifications made to this device that are not expressly approved by cypress semiconductor may void the user 's authority to oper ate the equipment. this equipment has been tested and found to comply with the limi ts for a class b digital device, pursuant to part 15 of the fcc rules. these limits are designed to provide reas onable protection against harmful interferenc e in a residential installation. this equ ipment generates and can radiate radio frequency energy and, if not inst alled and used in accordance with the instructions, may cause harmful interference to radio communications. however, there is no guarantee that interference will not occur in a particular installat ion. if this equipment does cause harmful interference to radio or televisi on reception, which can be determined by turning the equipment of f and on, the user is encouraged to try to correct the in terference by one or more of the following measures: reorient or relocate the receiving antenna. increase the separation between the equipment and receiver. connect the equipment into an outlet on a circuit diff erent from that to which th e receiver is connected. consult the dealer or an experienced radio/tv technician for help labeling requirements: the original equipment manufacturer (oem) mu st ensure that fcc labelling requirements are met. this includes a clearly visible label on the outside of the oem enclosure s pecifying the appropriate cypress semiconduct or fcc identifier for this product as w ell as the fcc notice above. the fcc identifier is fcc id: wap4008. in any case the end product must be labeled exterior with "contains fcc id: wap4008" antenna warning: this device is tested with a standard sma connector and with the antennas listed in table 7 on page 14. when integrated in the oems product, these fixed antennas require installation preventing end-u sers from replacing them with non-approved antennas. any ant enna not in the following table must be tested to comply with fcc section 15.203 for unique antenna c onnectors and section 15.247 fo r emissions. rf exposure: to comply with fcc rf exposure requirements, the original eq uipment manufacturer (oem) must ensure to install the approved antenna in the previous. the preceding statement must be included as a caution statement in manuals, for pro ducts operating with th e approved antennas in table 7 on page 14, to alert users on fcc rf exposure compliance. any notification to the end user of installation or removal instructions about the integrated radio module is not allowed. the radiated output power of CYBLE-214015-01 is far below the fcc radio frequency exposure limits. nevertheless, use CYBLE-214015-01 in such a manner that minimizes th e potential for human contact during normal operation. end users may not be provided with the module installation instru ctions. oem integrators and end users must be provided with transmitter operating conditions for satisfying rf exposure compliance.
preliminary CYBLE-214015-01 document number: 002-15923 rev. *b page 33 of 42 industry canada (i c) certification CYBLE-214015-01 is licensed to meet the regu latory requirements of industry canada (ic), license: ic: 7922a-4008 manufacturers of mobile, fixed or portable devices incorporating this module are advised to clarify any regulatory questions an d ensure compliance for sar and/or rf exposure limits. users can obta in canadian information on rf exposure and compliance from www.ic.gc.ca. this device has been designed to operate with the antennas listed in table 7 on page 14, having a maximum gain of 0.5 dbi. antennas not included in this list or having a gain greater than 0.5 dbi are stri ctly prohibited for use with this device. the required antenna impedance is 50 ohms. the antenna used for this transmitter must not be co-located or operating in conjunction with any other a ntenna or transmitter. ic notice: the device CYBLE-214015-01 complies with canada rss-gen rules. the device meets the requirements for modular transmitter approval as detailed in rss-gen. operatio n is subject to the following two conditions: (1) this device may not cause harmful interference, and (2) this device must accept any interference received, including interference that may cause undesired operat ion. ic radiation exposure statement for canada this device complies with industry canada licence-exempt rss stand ard(s). operation is subject to the following two conditions: (1) this device may not cause interference, and (2) this device must accept any interference, including interference that may cause undesired operation of the device. le prsent appareil est conforme aux cnr d'industrie canada applic ables aux appareils radio exempts de licence. l'exploitation est autorise aux deux conditions suivantes : (1) l'appareil ne doit pas produire de brouillage, et (2) l'utilisateur de l'appareil doit accepter tout brouillage radiolectrique subi, mme si le brouillage est susceptible d'en compromettre le fonctionnement. labeling requirements: the original equipment manufacturer (oem) must ensure that ic labelling requirements are met. this includes a clearly visible l abel on the outside of the oem enclosure specifyi ng the appropriate cypress semiconductor ic identifier for this product as well as the ic notice above. the ic identifier is 7922a-4 008. in any case, the end product must be labeled in its exterior with "contains ic: 7922a-4008". european r&tte declaration of conformity hereby, cypress semiconductor declares that the bluetooth modu le CYBLE-214015-01 complies with t he essential requirements and other relevant provisions of directive 1999 /5/ec. as a result of the conformity asse ssment procedure described in annex iii of the directive 1999/5/ec, the end-customer equ ipment should be labeled as follows: all versions of the CYBLE-214015-01 in the specified reference design can be used in the following countries: austria, belgium, cyprus, czech republic, denmark, estonia, fi nland, france, germany, greece, hungary, ireland, italy, latvia, lithuania, luxem- bourg, malta, poland, portugal, slovakia, slovenia, spain, sweden, the netherlands, th e united kingdom, switzerland, and norway .
preliminary CYBLE-214015-01 document number: 002-15923 rev. *b page 34 of 42 mic japan CYBLE-214015-01 is certified as a module with type certification number 203-jn0505. end products that integrate CYBLE-214015-01 do not need additional mic japan certification for the end product. end product can display the certific ation label of the embedded module. kc korea CYBLE-214015-01 is certified for use in kor ea with certificate number msip-crm-cyp-4008.
preliminary CYBLE-214015-01 document number: 002-15923 rev. *b page 35 of 42 packaging the CYBLE-214015-01 is offered in tape and reel packaging. figure 10 details the tape dimensions used for the CYBLE-214015-01. figure 10. CYBLE-214015-01 tape dimensions figure 11 details the orientation of the CYBLE-214015-01 in the tape as well as the direction for unreeling. figure 11. component orientation in tape and unreeling direction table 56. solder reflow peak temperature module part number package maximum peak temperature maximum time at peaktemperature no. of cycles CYBLE-214015-01 32-pad smt 260 c 30 seconds 2 table 57. package moisture sensitivity level (msl), ipc/jedec j-std-2 module part number package msl CYBLE-214015-01 32-pad smt msl 3
preliminary CYBLE-214015-01 document number: 002-15923 rev. *b page 36 of 42 figure 12 details reel dimensions used for the CYBLE-214015-01. figure 12. reel dimensions the CYBLE-214015-01 is designed to be used with pick-and-plac e equipment in an smt manufacturing environment. the center-of-mass for the CYBLE-214015-01 is detailed in figure 13 . figure 13. CYBLE-214015-01 center of mass
preliminary CYBLE-214015-01 document number: 002-15923 rev. *b page 37 of 42 ordering information ta b l e 5 8 lists the CYBLE-214015-01 part number and features. ta b l e 5 9 lists the reel shipment quantities for the CYBLE-214015-01. table 59. tape and reel package quantity and minimum order amount the CYBLE-214015-01 is offered in tape and reel packaging. the CYBLE-214015-01 ships with a maximum of 500 units/reel. part numbering convention the part numbers are of the form cyble-abcdef- gh where the fields are defined as follows. for additional information and a complete list of cypress semiconductor ble products, contact your local cypress sales representative. to locate the nearest cypress office, visit our website. table 58. ordering information mpn features package max cpu speed (mhz) flash (kb) sram (kb) udb opamp (ctbm) capsense direct lcd drive 12-bit sar adc lp comparators tcpwm blocks scb blocks pwms (using udbs) i2s (using udb) gpio CYBLE-214015-01 48 256 32 4 4 ? ? 1 msps 1 4 2 4 ? 25 32-smt description minimum reel quantity maximum reel quantity comments reel quantity 500 500 ships in 500 unit reel quantities. minimum order quantity (moq) 500 ? order increment (oi) 500 ? u.s. cypress headquarters address 198 champion court, san jose, ca 95134 u.s. cypress headquarter contact info (408) 943-2600 cypress website address http://www.cypress.com
preliminary CYBLE-214015-01 document number: 002-15923 rev. *b page 38 of 42 acronyms table 60. acronyms used in this document acronym description abus analog local bus adc analog-to-digital converter ag analog global ahb amba (advanced microcontroller bus architecture) high-performance bus, an arm data transfer bus alu arithmetic logic unit amuxbus analog mu ltiplexer bus api application programming interface apsr application program status register arm ? advanced risc machine, a cpu architecture atm automatic thump mode ble bluetooth low energy bluetooth sig bluetooth special interest group bw bandwidth can controller area network, a communications protocol ce european conformity csa canadian standards association cmrr common-mode rejection ratio cpu central processing unit crc cyclic redundancy check, an error-checking protocol dac digital-to-analog converter, see also idac, vdac dfb digital filter block dio digital input/output, gpio with only digital capabilities, no analog. see gpio. dmips dhrystone million instructions per second dma direct memory access, see also td dnl differential nonlinearity, see also inl dnu do not use dr port write data registers dsi digital system interconnect dwt data watchpoint and trace ecc error correcting code eco external crystal oscillator eeprom electrically erasable programmable read-only memory emi electromagnetic interference emif external memory interface eoc end of conversion eof end of frame epsr execution program status register esd electrostatic discharge etm embedded trace macrocell fcc federal communications commission fet field-effect transistor fir finite impulse resp onse, see also iir fpb flash patch and breakpoint fs full-speed gpio general-purpose input/output, applies to a psoc pin hci host controller interface hvi high-voltage interrupt, see also lvi, lvd ic integrated circuit idac current dac, see also dac, vdac ide integrated development environment i 2 c, or iic inter-integrated circuit, a communications protocol ic industry canada iir infinite impulse response, see also fir ilo internal low-speed oscillator, see also imo imo internal main oscillator, see also ilo inl integral nonlinearity, see also dnl i/o input/output, see also gpio, dio, sio, usbio ipor initial power-on reset ipsr interrupt program status register irq interrupt request itm instrumentation trace macrocell kc korea certification lcd liquid crystal display lin local interconnect network, a communications protocol. lr link register lut lookup table lvd low-voltage detect, see also lvi lvi low-voltage interrupt, see also hvi lvttl low-voltage transistor-transistor logic table 60. acronyms us ed in this document (continued) acronym description
preliminary CYBLE-214015-01 document number: 002-15923 rev. *b page 39 of 42 mac multiply-accumulate mcu microcontroller unit mic ministry of internal affairs and communications (japan) miso master-in slave-out nc no connect nmi nonmaskable interrupt nrz non-return-to-zero nvic nested vectored interrupt controller nvl nonvolatile latch, see also wol opamp operational amplifier pal programmable array logic, see also pld pc program counter pcb printed circuit board pga programmable gain amplifier phub peripheral hub phy physical layer picu port interrupt control unit pla programmable logic array pld programmable logic device, see also pal pll phase-locked loop pmdd package material declaration data sheet por power-on reset pres precise power-on reset prs pseudo random sequence ps port read data register psoc ? programmable system-on-chip? psrr power supply rejection ratio pwm pulse-width modulator qdid qualification design id ram random-access memory risc reduced-instruct ion-set computing rms root-mean-square rtc real-time clock rtl register transfer language rtr remote transmission request rx receive sar successive approximation register sc/ct switched capaci tor/continuous time scl i 2 c serial clock table 60. acronyms used in this document (continued) acronym description sda i 2 c serial data s/h sample and hold sinad signal to noise and distortion ratio sio special input/output, gpio with advanced features. see gpio. smt surface-mount technology; a method for producing electronic circuitry in which the components are placed directly onto the surface of pcbs soc start of conversion sof start of frame spi serial peripheral interface, a communications protocol sr slew rate sram static random access memory sres software reset stn super twisted nematic swd serial wire debug, a test protocol swv single-wire viewer td transaction descriptor, see also dma thd total harmonic distortion tia transimpedance amplifier tn twisted nematic trm technical reference manual ttl transistor-transistor logic tuv germany: technischer berwachungs-verein (technical inspection association) tx transmit uart universal asynchronous transmitter receiver, a communications protocol udb universal digital block usb universal serial bus usbio usb input/output, psoc pins used to connect to a usb port vdac voltage dac, see also dac, idac wdt watchdog timer wol write once latch, see also nvl wres watchdog timer reset xres external reset i/o pin xtal crystal table 60. acronyms us ed in this document (continued) acronym description
preliminary CYBLE-214015-01 document number: 002-15923 rev. *b page 40 of 42 document conventions units of measure table 61. units of measure symbol unit of measure c degrees celsius db decibel dbm decibel-milliwatts ff femtofarads hz hertz kb 1024 bytes kbps kilobits per second khr kilohour khz kilohertz k ? kilo ohm ksps kilosamples per second lsb least significant bit mbps megabits per second mhz megahertz m ? mega-ohm msps megasamples per second a microampere f microfarad h microhenry s microsecond v microvolt w microwatt ma milliampere ms millisecond mv millivolt na nanoampere ns nanosecond nv nanovolt ? ohm pf picofarad ppm parts per million ps picosecond s second sps samples per second sqrthz square root of hertz vvolt
preliminary CYBLE-214015-01 document number: 002-15923 rev. *b page 41 of 42 document history page document title: CYBLE-214015-01 ez-ble? psoc ? bluetooth 4.2 module document number: 002-15923 revision ecn orig. of change submission date description of change ** 5428716 dso 09/07/2016 preliminary dat asheet for CYBLE-214015-01 module. *a 5536076 dso 11/29/2016 updated more information : added ez-serial? ble firmware platform section. updated overview : updated figure 1 to specify that bottom view is ?seen from bottom?. updated recommended host pcb layout : updated figure 4 , figure 5 , and figure 6 captions to specify that these as ?seen on host pcb?. updated power supply connections and recommended external components : updated figure 7 and figure 8 to specify that these are ?seen from bottom?. updated digital and analog capabilities and connections : updated ta b l e 4 : updated tcpwm column to add tcpwm capability on port 2 pins. added footnote 3. updated document history page : remove ?,? from document title. *b 5554670 dso 12/15/2016 updated ta b l e 5 : port 2.x opamp definitions chan ged to ctbm0 instead of ctbm1. updated power supply connections and recommended external components : updated typo to state that the use of o ne to three ferrite beads will depend on the application configuration.
preliminary CYBLE-214015-01 document number: 002-15923 rev. *b revised december 15, 2016 page 42 of 42 ? cypress semiconductor corporation 2016. this document is the property of cypress semiconductor corporation and its subsidiari es, including spansion llc ("cypre ss"). this document, including any software or firmware included or referenced in this document ("software"), is owned by cypress under the intellectual prope rty laws and treaties of the united states and other countries worldwide. cypress reserves all rights under such laws and treaties and does not, except as specifically stated in this paragraph, grant a ny license under its patents, copyrights, trademarks, or other intellectual property rights. if the software is not accompanied by a license agreement and you do not otherwise have a written agreement w ith cypress governing the use of the software, then cypress hereby grants you under its copyright rights in the software, a personal, non-exclusive, nontransferable license (without the right to sublicense) (a) for software provided in source code form, to modify and reproduce the software solely for use with cypress hardware products, only internally within your organization, and (b) to dist ribute the software in binary code form externally to end users (either directly or indirectly through resellers and distributors), solely for use on cypress hardware product units. cypress also gran ts you a personal, non-exclusive, nontransferable, license (without the right to sublicense) under those claims of cypress's patents that are infringed by the software (as provided by cypress, unmodified) to make, use, distribute, and import the software solely to the minimum extent that is necessary for you to exercise your rights under the copyright license granted in the previous sentence. any oth er use, reproduction, modification, translation, or compilation of the software is prohibited. cypress makes no warranty of any kind, express or implied, with regard to this document or any software, including, but not lim ited to, the implied warranties of merchantability and fitness for a particular purpose. cypress reserves the right to make changes to this document without further notice. cypress does not assume any liability arising out of the application or use of any product or circuit described in this document. any informati on provided in this document, including any sample design information or programming code, is provided only for reference purposes. it is the responsibility of the user of this document to properly d esign, program, and test the functionality and safety of any application made of this information and any resulting product. cypress products are not designed, intended, or authorized for use as crit ical components in systems designed or intended for the operation of weapons, weapons systems, nuclear installati ons, life-support devices or systems, othe r medical devices or systems (including r esuscitation equipment and surgical implants), pollution control or hazardous substances management, or other uses where the failure of the device or system could cause personal injury, death, or property damage ("unintended uses"). a critical component is any component of a device or system whose failure to perform can be reasonably expected to cause the failure of the device or syste m, or to affect its safety or effectiv eness. cypress is not liable, in whole or in part, and company shall and hereby does release cypress from any claim, damage, or other liability arising from or relate d to all unintended uses of cypress products. company shall indemnify and hold cypress harmless from and against all claims, costs, damages, and other liabilities, including claims for personal inj ury or death, arising from or related to any unintended uses of cypress products. cypress, the cypress logo, spansion, the spansion logo, and combinations thereof, wiced, psoc, capsense, ez-usb, f-ram, and tra veo are trademarks or registered trademarks of cypress in the united states and other countries. for a more complete li st of cypress trademarks, visit cypress.com. other names and bra nds may be claimed as property of their respective owners. sales, solutions, and legal information worldwide sales and design support cypress maintains a worldwide network of offices, solution center s, manufacturer?s representatives, and distributors. to find t he office closest to you, visit us at cypress locations . products arm ? cortex ? microcontrollers cypress.com/arm automotive cypress.com/automotive clocks & buffers cypress.com/clocks interface cypress.com/interface internet of things cypress.com/iot memory cypress.com/memory microcontrollers cypress.com/mcu psoc cypress.com/psoc power management ics cypress.com/pmic touch sensing cypress.com/touch usb controllers cypress.com/usb wireless connectivity cypress.com/wireless psoc ? solutions psoc 1 | psoc 3 | psoc 4 | psoc 5lp cypress developer community forums | wiced iot forums | projects | video | blogs | training | components technical support cypress.com/support

▲Up To Search▲

Price & Availability of CYBLE-214015-01

	To Download CYBLE-214015-01 Datasheet File
If you can't view the Datasheet, Please click here to try to view without PDF Reader .